Integrated circuits are commonly electrically tested during integrated circuit manufacturing. During the electrical testing, electrical probes may be used to establish electrical contact between exposed or external electrical contacts of the integrated circuit under test and manufacturing test equipment. Terminal ends of the electrical probes may be contacted with the exposed electrical contacts, and then electrical signals may be exchanged between the manufacturing test equipment and the integrated circuit under test according to a test protocol.
In order to provide good contact, the size of the probes generally depends upon the size and/or the spacing (e.g., the pitch) of the exposed electrical contacts of the integrated circuits. In addition, there is a trend toward ever smaller electrical contacts and ever smaller spacing between the electrical contacts. One challenge is that, as the cross sectional area of the electrical probes decrease, the current carrying capacity of the electrical probes also generally decreases. The current carrying capacity generally represents the amount of current the electrical probes can carry without physical damage. When the cross sections of the electrical probes are too small for the current they are expected to carry, the amount of heat generated by resistance may cause the temperature of the electrical probes to increase to a point that damage occurs (e.g., melting, oxidation or other damaging reaction, etc.).
One approach to attempt to address this problem is to use tungsten, tungsten alloy, or other refractory metal or refractory metal alloy as the material of the electrical probes. These materials generally tend to have relatively high yield strength at high temperatures. However, these materials also generally tend to have relatively low electrical and thermal conductivities, which tend to counteract the benefit of the relatively high yield strength.
Another approach to attempt to address this problem is to form electrical probes as a micro-electro-mechanical system (MEMS) by a lithographic process involving lithographic patterning of a photoresist and development together with chemical and/or physical deposition processes. Stacks of two different materials may be formed alternately one layer over the other in a sandwich-like structure. One of the two materials may have a relatively high yield strength and another of the two materials may have relatively high electrical and thermal conductivities. However, drawbacks to this approach include relatively high manufacturing costs and relatively long assembly lead times, especially for relatively small cross sections.